1. Field of the Invention
The present invention is related to a pattern verifying method, and more particularly, to a pattern verifying method that is used in double pattern technology (DPT) process.
2. Description of the Prior Art
In semiconductor manufacturing processes, in order to transfer an integrated circuit layout onto a semiconductor wafer, the integrated circuit layout is first designed and formed as a photo-mask pattern. The photo-mask pattern is then proportionally transferred to a photoresist layer positioned on the semiconductor wafer.
In recent years, with the increasing miniaturization of semiconductor devices, the design rule of line width and space between lines or devices becomes finer. However, the width is subject to optical characteristics. To obtain fine-sized devices in the exposure, the interval between transparent regions in a mask is scaled down with device size. When the light passes through the mask, diffraction occurs and reduces resolution. Moreover, when light passes through the transparent regions of a mask having different interval sizes, the light through the regions having small interval sizes is influenced by the transparent regions having large interval sizes and results in deformation of the transfer pattern.
A double-exposure technique has been developed in recent years. The double-exposure technique involves decomposing a target pattern into two separated patterns, which are then transferred to a photoresist layer respectively by two exposure processes. Since the pitch of the decomposed pattern is larger, the pattern can be formed by current exposure systems. However, there are still some problems needed to be overcome in the double-exposure technique.